Marvell Blogs

Marvell Newsroom

Posts Tagged 'Networking'

  • September 22, 2026

    Is Memory the New Network? Inside the First MemNetAI Workshop at SIGCOMM

    By Abed Mohammad Kamaluddin, Director, Custom Cloud Solutions, Marvell, and Vienna Alexander, Marketing Content Professional, Marvell

    Is Memory the New Network? Inside the First MemNetAI Workshop at SIGCOMM

    For most of the last decade, scaling AI meant scaling compute. If you built faster accelerators and wired enough of them together, the models would follow.

    That is no longer the whole picture. Models now run to hundreds of billions of parameters with extensive context windows, and whether an expensive accelerator is working or just waiting comes down to memory: how much you have, how fast you can reach it, and how much time you lose moving data around.

    Once memory leaves the server and rides a switched fabric, is it still memory, or has it become a network? This was the central question of MemNetAI, the first workshop on Memory-Semantic Networking for AI-Scale Systems, launched by Marvell with researchers from IIT Hyderabad and IIIT Delhi. Held at ACM SIGCOMM 2026 in Denver and guided by a program committee spanning academia and industry, it brought speakers from Cornell, alongside industry experts and researchers presenting their work, to debate these questions on the bleeding edge of AI infrastructure.

  • June 24, 2026

    Structera X and A CXL Compression: Making Every Gigabyte Count

    By Arifur Rahman, Director of Product Marketing, Custom Cloud Solutions, Marvell

    Modern AI workloads are insatiable consumers of memory. Deep learning recommendation models (DLRM), large language model (LLM) inference, in-memory databases and vector search engines all share a common bottleneck: there is never enough DRAM, and what exists is very expensive.

    At today's spot prices—$27–$37 per GB for server-grade DDR5 RDIMMs1—a 12TB memory pool requires nearly half a million dollars in DRAM alone. Meanwhile, AI infrastructure buildouts are consuming server DRAM capacity faster than fabs can produce it, driving prices up 300–400% since mid-2025.1, 2

    CXL memory expansion was supposed to solve this. And it does—but there's a subtler lever that most solutions ignore: the data sitting in that memory is compressible, and most CXL controllers don't touch it.

  • June 17, 2026

    Plasmonics: A Path to Higher Bandwidth in Optics in the AI Era

    By Claudia Hoessbacher, Senior Director, and Wolfgang Heni, Director, Optical Engineering, Marvell

    Plasmons have been used to accelerate drug discovery, enhance the sensitivity of sensors and even create artistic treasures in the Roman era.

    Ongoing research at Marvell seeks to harness them to improve the performance of optical networks for the AI era. Plasmonics, a technology that leverages the properties of surface plasmon polaritons (SPPs), provides a promising pathway for enhancing the roadmap of silicon photonic (SiPho) light engines, a critical component inside optical modules.

    Plasmonic-based SiPho light engines could support modules operating at 3.2T and beyond while consuming a fraction of the space and power per bit of modules based on existing technologies. Manufacturers could leverage foundry process technologies for scaling production.

  • May 28, 2026

    Open CPX Sets the Stage for More Flexible, Scalable Connectivity

    By George Hervey, Associate Vice President, Cloud Switch Marketing, Marvell

    Co-packaged connectivity is coming. The Open CPX MSA (Co-packaging Multisource Agreement) is working to simplify adoption.

    The consortium, which includes Marvell and other leaders in connectivity, is developing specifications and standards for solutions for integrating near-packaged optical (NPO) and/or co-packaged optical (CPO) technology into switches and servers in scalable, repeatable ways. Members are also working to support interoperability with co-packaged copper (CPC).

    The idea is to give data center service providers, equipment manufacturers and others a unified framework for next-generation connectivity to accelerate innovation and meet the surging demand for these technologies. Fewer than one million near- and co-packaged ports shipped in 2025, according to LightCounting; by 2030, shipments are projected to surpass 100 million ports per year.1 Standards that can ensure predictability and flexibility will be critical in enabling this expected growth.

    “The initial target of the MSA will be to develop an optimized optical engine with a defined pluggable socket and electrical connector system supporting high speed and high-density connectivity between a switch or processor and co-packaged and near-package interconnects,” the Open CPX MSA website states. “The specifications will define connector mechanicals, thermals, electrical pinout, mechanical form factors, electrical, optical, and management interface specifications to ensure interoperability between multiple vendors of Open CPX.”

  • October 14, 2025

    AI Scale Up Goes for Distance with 9-meter 800G AEC from Infraeo and Marvell

    By Winnie Wu, Senior Director Product Marketing at Marvell

    Welcome to the beginning of row-scale computing.

    At the 2025 OCP Global Summit, Marvell and Infraeo will showcase a breakthrough in high-speed interconnect technology — a 9-meter active electrical cable (AEC) capable of transmitting 800G across standard copper. The demonstration will take place in the Marvell booth #B1.

    This latest innovation brings data center architecture one step closer to full row-scale AI system design, allowing copper connections that stretch across seven racks - that’s nearly the length of a standard 10-rack row. It builds on the prior achievement by Marvell of a 7-meter AEC demonstrated at OFC 2025, pushing high-speed copper technology even further beyond what was thought possible.

    Pushing the Boundaries of Copper

    Until now, copper connections in large-scale AI systems have been limited by reach. Traditional electrical cables lose signal quality as distance increases, restricting system architects to a few meters between servers or racks. The 9-meter AEC changes that equation.

    By combining high-performance digital signal processing (DSP) with advanced noise reduction and signal integrity engineering, the new design extends copper’s effective range well beyond conventional limits, maintaining clean, low-latency data transfer over distances once thought achievable only with optical fiber.

Archives