Modern AI workloads are insatiable consumers of memory. Deep learning recommendation models (DLRM), large language model (LLM) inference, in-memory databases and vector search engines all share a common bottleneck: there is never enough DRAM, and what exists is very expensive.

At today's spot prices—$27–$37 per GB for server-grade DDR5 RDIMMs1—a 12TB memory pool requires nearly half a million dollars in DRAM alone. Meanwhile, AI infrastructure buildouts are consuming server DRAM capacity faster than fabs can produce it, driving prices up 300–400% since mid-2025.^{1, 2}

CXL memory expansion was supposed to solve this. And it does—but there's a subtler lever that most solutions ignore: the data sitting in that memory is compressible, and most CXL controllers don't touch it.

Marvell does. At the heart of every Marvell Structera CXL^TM device is a purpose-built hardware block called the Compression-Decompression Block (CDB).

The CDB is not a software library or an optional firmware feature. It is dedicated silicon, running at full memory bandwidth, that transparently compresses data as it is written to DRAM and decompresses it as it is read, completely invisible to the host CPU and operating system. As a result, the host sees more memory than physically exists on the device.

The economic case is straightforward. Memory is the single largest cost component of a CXL memory pool. If you can compress data at 2:1, you effectively halve the cost per GB of useful capacity without buying more DIMMs, changing the server or modifying the application.

The Industry-first Moment

Structera products are the first in the industry to incorporate hardware-based inline memory compression adhering to the specifications submitted to the Open Compute Project (OCP). No other CXL memory controller vendor offers inline compression as a production feature today.³

The CDB uses a custom-implemented derivative of the LZ4 compression algorithm—a lossless algorithm chosen specifically for its balance of high compression ratio and ultra-low latency. LZ4 is a streaming, byte-oriented algorithm widely used in databases (RocksDB, ClickHouse), AI frameworks, and file systems precisely because it decompresses faster than memory bandwidth.

One of the CDB's most powerful features is one-to-many memory mapping; the host can be presented with a virtual address range larger than the physical DRAM by configuring an expected compression ratio. The CDB can be configured during build time, boot time or run time.

Key Performance Results: Structera X 2404/2504

Compression Ratios on Structera X/A

The industry-standard mixed real-world data types achieve the following ratios on Structera hardware, which matches or closely approaches host LZ4 ratios:

The Structera CDB matches host-side LZ4 compression quality, removing the need for software-based compression and freeing up host computing resources.

The Bottom Line

The Marvell® Structera Compression-Decompression Block is a silicon investment that changes the economics of CXL memory. By compressing data at line rate, in hardware and with zero host CPU involvement, the CDB turns every gigabyte of physical DRAM into two, four, or eight gigabytes of useful memory capacity.

At a time when DDR5 server memory costs $30 to $40 per GB and AI workloads are doubling their memory requirements every 18 months, the CDB may be the most important differentiator in the CXL market today.

1. Trendforce, DRAM Spot Price, April 2026
2. Sourceability Newsletter, Tracking memory price increases across the last several quarters, March 2026
3. Marvell, Structera CXL Product Line Announcement, July 2024

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