Scale up

Two elements of scale-up networking: switching and interconnect

Scale-up connectivity has two elements, the same two behind every tier of the AI data center: the switching that ties the domain together into a fabric, and the interconnect that carries the signal between accelerators and switches. Switching comes down to a protocol. Interconnect comes down to a type: first copper or optical, then, for optical links, which kind of optics. Marvell builds silicon across all of it.

Which switching protocols does scale-up networking use?

The switching layer ties a scale-up domain together, and it runs on a protocol. Several are in play, and the industry hasn't settled on which will win. PCIe is in limited use today based upon widespread use in other applications. UALink and ESUN are newer open standards, built specifically for scale up, with switches maturing. Ethernet is filling in as a bridge until those are ready. NVLink is the most widespread use today, supported by Marvell through NVLink Fusion. Each one trades off bandwidth, latency, openness, and how ready it is to deploy. Different operators are making different choices based on their own architectures and priorities.

Marvell is developing the broadest range of scale-up switches in the industry, spanning these protocols in a single portfolio. So, an operator can pick whichever protocol fits the system and build it with Marvell silicon. That same portfolio spans merchant, semi-custom, and custom silicon, so it fits an operator buying a standard part as well as a hyperscaler co-designing its own XPU.

Ethernet plays a specific role today. UALink and ESUN switches are still maturing, so some operators run scale-up traffic over Ethernet now, often by encapsulating a protocol like UALink over Ethernet until native switches arrive. Ethernet is the bridge; ESUN is where Ethernet is headed for scale up. The Marvell® Teralynx® T100 switch fills the bridge role today: 102.4 Tbps of low-latency switching, the same switch silicon used in scale-out fabrics, applied to the scale-up domain.

Marvell can also build to NVLink Fusion, supplying NVLink Fusion-compatible scale-up connectivity and custom XPUs. It's one supported path among several.

Scale-up interconnect: copper inside the rack, optics across racks

Where switching comes down to a protocol, interconnect comes down to a media type with two separate choices.

Copper carries the scale-up domain today

The first choice is the choice of physical media: copper or optical (fiber-optic cable). Inside the rack, copper carries data in the scale-up domain today at low power and low latency over the meter or two between accelerators. What makes a copper link fast is the electrical SerDes at each end. SerDes is  — the signaling technology that drives the data across the wire, engineered at the scale-in layer beneath every node.

As a scale-up domain pushes to the limits of copper reach, co-packaged copper (CPC) extends it one more step. CPC drives signals with the same 224G SerDes straight from the package to the cable, skipping the loss of traditional board routing—the highest signal integrity and lowest power per bit inside the rack. It's the last copper packaging step before a link has to go optical.

Optics take the domain across racks.

Past that point, the longer links of a multi-rack domain have to go optical to hold the bandwidth and latency scale up needs. How the optics get built isn't settled either, so Marvell is developing several photonic approaches in parallel—Marvell® Photonic Fabric® technology, built using electro-absorption modulators (EAM), is one approach, alongside Mach-Zehnder modulators (MZM), micro-ring modulators (MRM), micro-LED, micro-VCSEL, and others. Each is instantiated as a photonic I/O chiplet. 

Marvell Photonic Fabric technology extends a scale-up domain well past copper's reach while holding scale-up performance—high bandwidth, low latency, and low power over distances copper can't span. The same technology carries an optical shared-memory tier across racks. 

Where the optics sit is a separate choice

One more choice sits alongside these, independent of protocol and optical technology: where the optics physically go. Optics can sit on the board (on-board optics, OBO), move onto the interposer next to the package (near-package optics, NPO), or go inside it (co-packaged optics, CPO). The tightest, densest scale-up links are where co-packaging pays off, placing a photonic chiplet beside the compute silicon. That's why the natural home for co-packaged optics is the scale-up domain, while pluggable optical modules lead the scale-out fabric.

How does scale-up networking handle memory? 

Scale up connects accelerators; it also determines how memory is shared across them. As models grow—longer context windows, larger KV caches—memory capacity and bandwidth become as much a constraint as compute, and the scale-up domain has to let memory scale more independently. Marvell addresses this at two levels of the domain.

At rack level, Marvell® Structera™ X memory expansion solutions expand and pool CXL memory across servers, so operators can grow and share memory capacity without over-provisioning each server, laying the groundwork for CXL-based memory pooling and sharing.

Across multiple racks, the Marvell Photonic Fabric memory modules, Photonic Fabric NIC, and Photonic Fabric chiplets form an optical shared-memory tier that reaches multiple XPUs and racks up to 50 meters. It offloads up to 32TB of warm KV cache at high bandwidth and low latency, which can raise token throughput by up to 3x within the same data center footprint and power envelope.