AI infrastructure depends on memory bandwidth, capacity, latency, and power efficiency. As models grow and inference becomes more memory-intensive, the memory hierarchy increasingly determines XPU utilization and system performance.
Marvell helps hyperscalers, data center builders, and cloud providers design memory across the system, from custom SRAM and HBM near compute to CXL-based expansion, pooling, shared memory, and near-memory acceleration.
CXL provides a standards-based foundation for adding and sharing memory beyond the CPU or XPU. Marvell can shape the controller and surrounding subsystem around specific capacity, bandwidth, security, software, form-factor, and deployment requirements.
Technology Building Blocks for AI Accelerator Design
Dense SRAM
Deliver Local Bandwidth Where Compute Needs It
Deliver Local Bandwidth Where Compute Needs It
AI accelerators rely on on-chip memory for activations, buffers, queues, metadata, tables, and intermediate results. Memory architecture directly affects bandwidth, power, and die area.
Marvell custom SRAM can be optimized around the workload and floorplan, including width, depth, ports, timing, clocking, voltage behavior, aspect ratio, redundancy, and repair.
- High-capacity embedded memory: Supports up to 6 Gb of high-speed SRAM.
- Area efficiency: Recovers up to 15% of total die area compared with standard implementations.
- Lower standby power: Reduces standby power by up to 66%.
The result is more local bandwidth with lower memory overhead.
Custom HBM with D2D
Increase Compute and Memory Within the Package
Increase Compute and Memory Within the Package
Scaling multi-die accelerators requires massive bandwidth between compute, memory, and I/O dies without exhausting power budgets or die-edge real estate. Marvell 2nm D2D IP delivers breakthrough efficiency.
- Massive bandwidth density: Achieves over 30 Tbps/mm (more than 3X the density of UCIe at equivalent speeds), with 64 Gbps per wire bidirectional signaling.
- Exceptional power savings: Delivers up to 75% lower interface power under normal workloads and up to 42% lower at peak.
- Built-in resilience: Features redundant lanes and automatic lane repair for maximum reliability.
By reducing the power and area required to move data between dies, Marvell die-to-die technology gives architects greater flexibility to partition accelerator functions across the package.
Custom CXL Memory Expansion and Pooling
Add Capacity Beyond Local Memory Limits
Add Capacity Beyond Local Memory Limits
CXL allows memory capacity to extend beyond the DRAM directly attached to a CPU or XPU. It also enables new approaches to pooling, sharing, and disaggregation.
Marvell can develop custom CXL memory controllers and subsystems around the required topology, bandwidth, capacity, memory media, security, software, and deployment model. For standard deployment requirements, Marvell also offers the Structera family of CXL memory expansion, pooling, and acceleration products.
- Memory Expansion: Add DDR capacity beyond local CPU or XPU memory. Controller architecture can be optimized around memory channels, compression, security, telemetry, and form factor.
- Memory Pooling: Share capacity across multiple hosts or accelerators to improve utilization and reduce stranded memory. CXL 3.0 provides the foundation for broader rack-scale memory fabrics.
- Optical Shared Memory: Use Marvell Photonic Fabric to extend memory connectivity beyond electrical reach and support shared or disaggregated memory across multiple racks.
- Workload-Specific CXL: Combine CXL with customer-specific controller functions, including compression, security, embedded compute, management, firmware, and software integration.
Memory Acceleration and Near-Memory Compute
Process More Data Closer to Memory
Process More Data Closer to Memory
Moving large data sets between memory and processors consumes bandwidth and power. Memory acceleration places selected functions in the memory path so more work can be completed closer to the data.
Marvell can integrate:
- Compression and encryption
- Data movement
- Command processing
- Embedded compute
- Firmware
- Workload-specific acceleration
These capabilities can increase effective capacity, reduce host processing, and lower traffic across the memory fabric.
Resources
Marvell Demonstrates Scalable CXL Memory Infrastructure with Intel
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Marvell Structera X Extends CXL Interoperability to NVIDIA Vera
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Boosting AI with CXL Part III: Faster Time-to-First-Token
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Custom Memory Solutions FAQs
What is a custom memory solution?
A custom memory solution changes part of the memory architecture around the requirements of a specific workload or system. Customization can occur in the embedded memory, HBM base die, memory interface, controller, protocol, form factor, compression, security, firmware, software, or system integration. It does not require every component in the memory subsystem to be proprietary.
When is an off-the-shelf memory product the better choice?
A merchant product is usually the better choice when its interface, capacity, memory support, form factor, feature set, software model, and deployment schedule already meet the requirements.
Customization becomes more valuable when those constraints begin limiting performance, utilization, power, capacity, or system economics.
Is Custom Memory the same as Structera?
No. Structera is the Marvell merchant CXL product family for memory expansion, pooling, and near-memory acceleration. Custom Memory Products is the broader custom category. Structera can be a proof point, reference architecture, or starting point, but a custom memory engagement is shaped around the customer’s XPU, server, rack, software stack, workload, and roadmap.
Does custom memory mean proprietary memory?
No. Custom Memory can use standard interfaces such as CXL or PCIe. The customization may be in the controller behavior, feature set, media strategy, software hooks, security, telemetry, form factor, or system integration.
How does Custom Memory help with XPU bandwidth?
Custom SRAM increases local bandwidth on the die. Custom HBM with D2D improves package-level bandwidth and reduces interface overhead. Memory acceleration and near-memory compute help reduce unnecessary data movement.
What is memory pooling?
Memory pooling allows capacity to be shared across multiple processors or accelerators, improving utilization and reducing stranded memory.
Where does Photonic Fabric fit?
Photonic Fabric extends high-bandwidth memory connectivity beyond electrical reach, supporting shared and disaggregated memory architectures across racks.
What is near-memory compute
Near-memory compute places processing closer to large memory resources to reduce data movement and host processing.
How does Custom Memory help with capacity?
CXL-based memory expansion adds DDR capacity beyond local memory limits. Memory pooling makes capacity available across hosts and accelerators. Compression can increase effective memory capacity.
Where does Custom HBM fit?
Custom HBM fits at the package level, close to the XPU. It helps increase memory capacity and improve interface efficiency while returning more XPU area and power to compute.
Where does Custom SRAM fit?
Custom SRAM fits on the die, closest to compute. It supports high-bandwidth local structures such as caches, buffers, scratchpads, queues, metadata, and workload-specific state.
What is memory acceleration?
Memory acceleration adds functions such as compression, encryption, data movement, command processing, and embedded compute into the memory path. The goal is to make memory more useful than passive capacity.
When should a customer engage Marvell?
Early in architecture definition. Memory decisions affect XPU area, package layout, power, thermals, server design, software, supply chain, validation, and TCO.
The earlier Marvell engages, the more opportunity there is to shape the memory path around the workload.
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