AI and cloud infrastructure depend on specialized processors around the primary CPU or XPU to handle control, storage, media, security, and other supporting functions. Custom co-processors move these workloads onto purpose-built silicon so each function can be optimized for the performance, power, latency, security, and manageability requirements of the system.
Marvell develops custom co-processors as part of a broader infrastructure architecture, combining workload-specific processing with proven connectivity, memory, security, and interface technologies. Designs can range from focused controllers to highly integrated devices with dedicated acceleration, telemetry, and management capabilities.
This approach gives greater control over how supporting functions are implemented, how data moves through the system, and how the device connects with the rest of the infrastructure. Marvell supports architecture, implementation, validation, manufacturing, and volume deployment across a broad range of companion silicon for AI and cloud systems.
Custom Co-Processors from Marvell
Host and platform management processors
Host and platform management processors
Host and platform management processors
Host and platform management processors provide dedicated control and management for servers, accelerator systems, and AI infrastructure. They coordinate system initialization, monitor operating conditions, collect telemetry, manage faults, and support the control functions required to operate infrastructure reliably at scale. A custom device allows these capabilities to align with the system architecture, management environment, security model, and deployment requirements.
Capabilities include:
- System initialization, boot, and power sequencing
- Health monitoring, telemetry, and fault management
- Thermal, power, and platform control
- Management interfaces and control-plane processing
- Secure boot, device identity, and trusted management functions
- Custom firmware and management features
Marvell can combine dedicated processing with connectivity, security, memory, and interface IP to create a management processor designed from a system perspective.
Storage controllers and accelerators
Storage controllers and accelerators
Storage controllers and accelerators
Storage controllers and accelerators manage and offload data movement, processing, and protection between compute and storage resources. As storage bandwidth and capacity increase, dedicated silicon can reduce host-processing overhead while allowing storage functions to be optimized for specific infrastructure requirements. Custom storage processors can span traditional controller functions as well as higher-value acceleration and data-path processing.
Capabilities include:
- SSD and NVMe controller function
- Storage protocol and data-path processing
- Compression and data reduction
- Encryption and data protection
- Metadata and storage-management acceleration
- Near-storage processing and workload-specific offload
The architecture is shaped around the storage media, host interface, workload, performance targets, protection requirements, and software environment, helping teams build storage infrastructure with the throughput, efficiency, and control required at scale.
Media and video processors
Media and video processors
Media and video processors
Media and video processors provide dedicated compute for high-volume video and media workloads that would otherwise consume CPU, XPU, or system resources. Custom silicon allows processing pipelines to be aligned with specific codecs, resolutions, quality targets, throughput requirements, and deployment economics. This is especially valuable when large numbers of media streams must be processed predictably within defined power and cost envelopes.
Capabilities include:
- Video encode and decode
- Transcoding and format conversion
- Image and media processing
- Stream processing and pipeline acceleration
- Workload-specific media engines
- Memory and data-movement optimization
Internally developed technology can also be integrated with Marvell IP and third-party IP, giving greater control over performance, efficiency, feature integration, and the evolution of the media-processing roadmap.
Security processors
Security processors
Security processors
Security processors offload cryptographic, trust, and data-protection functions from the host CPU or XPU, allowing security to scale with the performance and deployment requirements of the broader system. A custom security processor can be designed around the system’s trust architecture, cryptographic requirements, compliance needs, management environment, and data flows instead of relying on a general-purpose security device.
Capabilities include:
- Cryptographic acceleration for encryption, decryption, signing, and authentication
- Key generation, storage, and lifecycle management
- Secure boot, attestation, and device identity
- Hardware security module functionality
- Root of trust and platform integrity
- Secure firmware update and recovery
- Security telemetry and policy enforcement
Marvell combines dedicated security processing with embedded compute, high-speed interfaces, memory, and management capabilities. This enables critical security functions to be implemented closer to the data path while reducing processing overhead on the primary compute resources.
Resources
CompanyNewsroomRelease Marvell Advances AI Memory Infrastructure Portfolio to Accelerate Agentic AI Inference
Learn More
Marvell and NVIDIA to Provide Custom Solutions for Advanced AI Infrastructure
Learn More
Custom Compute in the AI Era
Learn More
Custom Co-Processors FAQs
What is a custom co-processor?
A custom co-processor is a purpose-built processor that works alongside a CPU, XPU, or other primary compute device to handle a defined infrastructure workload. Examples include host management, storage processing, media acceleration, and security processing.
How is a co-processor different from an AI accelerator?
An AI accelerator performs the primary compute associated with AI training or inference. A co-processor handles supporting or specialized infrastructure functions that can be executed more efficiently outside the primary compute engine.
Why move these functions to a dedicated processor?
Dedicated silicon allows the function to be optimized independently for performance, power, latency, interfaces, memory, security, and software. It can also reduce the processing load placed on the host CPU or XPU.
When does a custom co-processor make sense?
A custom approach becomes more compelling when a function operates at significant scale, has workload-specific requirements, consumes substantial host resources, requires tighter system integration, or provides meaningful differentiation in performance, power, cost, security, or manageability.
How is a custom co-processor different from an off-the-shelf controller?
A standard device is designed for a broad set of requirements. A custom co-processor can be shaped around specific workload, interfaces, system architecture, firmware, security model, and deployment priorities. It can also consolidate functions that would otherwise require several standard components.
Can internally developed IP be incorporated?
Yes. Designs can combine internally developed technology with Marvell IP, third-party IP, open standards, and application-specific logic. The division of responsibility can be structured around specific capabilities and differentiation.
Can security be integrated into other types of co-processors?
Yes. Security functions such as secure boot, cryptographic acceleration, key management, device identity, and telemetry can be integrated into host management, storage, media, or other processors where the architecture requires them.
What interfaces can be supported?
Interface requirements depend on the application and can include PCIe, Ethernet, memory interfaces, die-to-die connectivity, and other high-speed or application-specific links. The Marvell connectivity portfolio can be brought into the architecture where appropriate.
Does Marvell support firmware and software?
Programs can include firmware, software, diagnostics, telemetry, validation, and bring-up support required for the device to operate within the broader infrastructure.
How does Marvell approach co-processor development?
Programs begin with the workload and system requirements. Marvell works collaboratively to define the processing architecture, interfaces, memory, security, software, packaging, and implementation strategy before moving through design, validation, bring-up, qualification, and volume production.
Contact Us
We believe better partnerships help to build better technologies. Let’s connect and see what we can design together!
Thank You for Your Interest
We will be in touch with you soon!
