DesignCon 2022

DesignCon 2022

See Marvell at DesignCon 2022

Panel Discussion:

Tuesday, April 5, 2022

Time: 4:45 pm - 6:00 pm

Location: Ballroom GH, Santa Clara Convention Center

Panel – The Case of the Closing Eyes: PAM-N, What Can be Tested?

Marvell Panelist: Mark Marlett, Sr. Principal System Engineer

The Case of the Closing Eyes is an opportunity for DesignCon attendees to learn about the challenges of new communications system design methodology from two distinct angles; the semiconductor industry and the test & measurement industry. The area of discussion is about bringing new technology to the communications industry using PHY layer validation techniques that are conclusive enough for widespread, error-free adoption. Participants will have an opportunity to engage in the open panelist debates and take insightful information back to their design labs.

Paper Presentations:

Wednesday, April 6, 2022

Time: 12:15 pm - 1:00 pm

Location: Ballroom D, Santa Clara Convention Center

Topic: Parametric System Model of a 112Gbps ADC-based SerDes for Architectural, Design & Validation Project Phases

Speaker: Aleksey Tyshchenko, SeriaLink Systems

Authors: David Halupka, SeriaLink Systems; Venu Balasubramonian, Marvell; Lenin Patra, Marvell

This paper presents a parametric ADC-based SerDes system modeling framework intended to support all project phases: from architectural definition, through analog and digital design, to validation.

Modeling techniques that enable a single model to support a wide range of system modeling activities are introduced. The parametrization of key design variables allows for the evaluation of architectural options to generate block level specifications. Object oriented modeling is used to decouple block interfaces from the evolving block implementation, thereby maintaining a simulation-ready top-level model. The block-level models support automated export to SystemVerlilog thereby facilitating mixed-signal design validation.

A correlation example is described to illustrate how the proposed modeling framework can be configured to reflect the IBIS-AMI model of a 112Gb/s ADC-based SerDes product.

In addition to being a valuable tool during SerDes development, these models can be delivered to system integrators enabling the incorporation of accurate models that capture the details of a real-life ADC-based SerDes right from the feasibility study phase. These models allow system integrators better observability and flexibility in performing end-to-end link analysis: including simulation of co-packaged and opto-electrical systems, and exploring interaction between SerDes and FEC. The underlying implementation can be obfuscated at different hierarchy levels for IP protection.

Wednesday, April 6, 2022

Time: 3:00 pm - 3:45 pm

Location: Ballroom G, Santa Clara Convention Center

Topic: Validation Shift-left: Enabling Early SerDes Mixed-signal Validation

Speakers: David Halupka, SeriaLink Systems; Aleksey Tyshchenko, SeriaLink Systems; Richard Allred, MathWorks, Inc.

Authors: Marc Erickson, MathWorks, Inc.; Tripp Worrell, MathWorks, Inc.; Barry Katz, MathWorks, Inc. / SiSoft; Jesson John, MathWorks, Inc.; Ranjan Sahoo, NXP Semiconductors; Lenin Patra, Marvell; Venu Balasubramonian, Marvell; Pragati Tiwary, MathWorks, Inc.

The completion of SerDes design validation is typically gated by the availability of SystemVerilog analog behavioral models. As data rates increase beyond 100Gb/s, transistor technologies scale, and design margins shrink, achieving analog design targets and predicting analog design completion is becoming increasingly difficult. This, in turn, delays the availability of behavioral models and degrades design verification quality. We present a methodology to automatically generate SystemVerilog behavioral models from SerDes system models, which are available prior to analog design completion. This approach alleviates analog design dependencies, thus shifting left the design validation timeline. As the analog design evolves, the system models are refined with simulation data, and the SystemVerilog models are refreshed to maintain design correlation.

会場へのアクセス

DesignCon 2022
Santa Clara Convention Center
April 5-7, 2022

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