Posts Tagged 'AI'
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October 14, 2025
AI Scale Up Goes for Distance with 9-meter 800G AEC from Infraeo and Marvell
By Winnie Wu, Senior Director Product Marketing at Marvell
Welcome to the beginning of row-scale computing.
At the 2025 OCP Global Summit, Marvell and Infraeo will showcase a breakthrough in high-speed interconnect technology — a 9-meter active electrical cable (AEC) capable of transmitting 800G across standard copper. The demonstration will take place in the Marvell booth #B1.
This latest innovation brings data center architecture one step closer to full row-scale AI system design, allowing copper connections that stretch across seven racks - that’s nearly the length of a standard 10-rack row. It builds on the prior achievement by Marvell of a 7-meter AEC demonstrated at OFC 2025, pushing high-speed copper technology even further beyond what was thought possible.
Pushing the Boundaries of Copper
Until now, copper connections in large-scale AI systems have been limited by reach. Traditional electrical cables lose signal quality as distance increases, restricting system architects to a few meters between servers or racks. The 9-meter AEC changes that equation.
By combining high-performance digital signal processing (DSP) with advanced noise reduction and signal integrity engineering, the new design extends copper’s effective range well beyond conventional limits, maintaining clean, low-latency data transfer over distances once thought achievable only with optical fiber.
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October 07, 2025
Faster, Farther and Going Optical: How PCIe Is Accelerating the AI Revolution
By Annie Liao, Product Management Director, ODSP Marketing, Marvell
For over 20 years, PCIe, or Peripheral Component Interconnect Express, has been the dominant standard to connect processors, NICs, drives and other components within servers thanks to the low latency and high bandwidth of the protocol as well as the growing expertise around PCIe across the technology ecosystem. It will also play a leading role in defining the next generation of computing systems for AI through increases in performance and combining PCIe with optics.
Here’s why:
PCIe Transitions Are Accelerating
Seven years passed between the debut of PCIe Gen 3 (8 gigatransfers/second—GT/s) in 2010 and the release of PCIe Gen 4 (16 GT/sec) in 2017.1 Commercial adoption, meanwhile, took closer to a full decade2
Toward a terabit (per second): PCIe standards are being developed and adopted at a faster rate to keep up with the chip-to-chip interconnect speeds needed by system designers.
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September 08, 2025
Connectivity for AI in the Million XPU Era
By Xi Wang, Senior Vice President and General Manager of Connectivity, Marvell
AI has been a huge catalyst for the adoption of connectivity in networks.
Already, operators are deploying AI data centers with over 200,000 GPUs—and they’re moving even faster towards 1 million XPUs. Driven by the increase in bandwidth and the growing size and number of clusters needed for AI applications, we are in a massive growth market for interconnect solutions. Accordingly, the optical interconnect global market has doubled since 2020 to nearly 20 billion dollars in 2025, and it is expected to double again by 2030, with an industry CAGR (Compound Annual Growth Rate) of about 18%.1
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August 13, 2025
Chiplets Turn 10: Here are Ten Things to Know
By Michael Kanellos, Head of Influencer Relations, Marvell
Chiplets—devices made up of smaller, specialized cores linked together to function like a unified device—have dramatically transformed semiconductors over the past decade. Here’s a quick overview of their history and where the design concept goes next.
1. Initially, they went by the name RAMP
In 2006, Dave Patterson, the storied professor of computer science at UC Berkeley, and his lab published a paper describing how semiconductors will shift from monolithic silicon to devices where different dies are connected and combined into a package that, to the rest of the system, acts like a single device.1
While the paper also coined the term chiplet, the Berkeley team preferred RAMP (Research Accelerator for Multiple Processors).
2. In Silicon Valley fashion, the early R&D took place in a garage
Marvell co-founder and former CEO Sehat Sutardja started experimenting with combining different chips into a unified package in the 2010s in his garage, according to journalist Junko Yoshida.2 In 2015, he unveiled the MoChi (Modular Chip) concept, often credited as the first commercial platform for chiplets, in a keynote at ISSCC in February 2015.3
The first products came out a few months later in October.
“The introduction of Marvell’s AP806 MoChi module is the first step in creating a new process that can change the way that the industry designs chips,” wrote Linley Gwennap in Microprocessor Report.4
An early MoChi concept combining CPUs, a GPU and a FLC (final level cache) controller for distributing data across flash and DRAM for optimizing power. Credit: Microprocessor Forum.
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August 06, 2025
Three New Technologies for Raising the Performance Ceiling on Custom Compute
By Michael Kanellos, Head of Influencer Relations, Marvell
More customers, more devices, more technologies, and more performance—that, ultimately, is where custom silicon is headed. While Moore’s Law is still alive, customization is taking over fast as the engine for driving change, innovation and performance in data infrastructure. A growing universe of users and chip designers are embracing the trend and if you want to see what’s at the cutting edge of custom, the best chips to study are the compute devices for data centers, i.e. the XPUs, CPUs, and GPUs powering AI clusters and clouds. By 2028, custom computing devices are to account for $55 billion in revenue, or 25% of the market.1 Technologies developed for this segment will trickle down into others.
Here are three of the latest innovations from Marvell:
Multi-Die Packaging with RDL Interposers
Achieving performance and power gains by shrinking transistors is getting more difficult and expensive. “There has been a pretty pronounced slowing of Moore’s Law. For every technology generation we don’t get the doubling (of performance) that we used to get,” says Marvell’s Mark Kuemerle, Vice President of Technology, Custom Cloud Solutions. “Unfortunately, data centers don’t care. They need a way to increase performance every generation.”
Instead of shrinking transistors to get more of them into a finite space, chiplets effectively allow designers to stack cores on top of each other with the packaging serving as the vertical superstructure.
2.5D packaging, debuted by Marvell in May, increases the effective amount of compute silicon for a given space by 2.8 times.2 At the same time, the RDL interposer wires them in a more efficient manner. In conventional chiplets, a single interposer spans the floor space of the chips it connects as well as any area between them. If two computing cores are on opposite sides of a chiplet package, the interposer will cover the entire space.
Marvell® RDL interposers, by contrast, are form-fitted to individual computing die with six layers of interconnects managing the connections.
2.5D and multilayer packaging. With current manufacturing technologies, chips can achieve a maximum area of just over 800 sq. mm. By stacking them, the total number of transistors in an XY footprint can grow exponentially. Within these packages, RDL interposers are the elevator shafts, providing connectivity between and across layers in a space-efficient manner.
Recent Posts
- AI Scale Up Goes for Distance with 9-meter 800G AEC from Infraeo and Marvell
- Faster, Farther and Going Optical: How PCIe Is Accelerating the AI Revolution
- Marvell Wins Leading EDGE Award for Ara 1.6T Optical DSP
- Connectivity for AI in the Million XPU Era
- Marvell Ranks on the A-List of CDP Supplier Engagement Leaders
