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Join Marvell at the 28th IEEE International Symposium on VLSI Design and Test (VDAT) 2024
The IEEE International Symposium provides opportunities for academia, researchers, startups, and industrial practitioners to share new ideas, experiences, and knowledge in various fields of VLSI Design and Testing.
Presentation
Tutorial Track: Standard cell characterization
Topic: Life cycle and development of custom Standard cells
Date: Sunday, September 1, 2024
Time: 9:30 a.m.
Marvell Presenter: Aquib Quraishi, Staff Engineer
Tutorial Track
Topic: Impact of Design for Test on the Production of a Chip
Date: September 1, 2024
Time: 11.30 a.m.
Marvell Presenters: Aanand Venkatachalam, Director and Suraj Chathoth, Principle Engineer
Keynote: Transforming Cloud Infrastructure for the AI era
Date: Monday, September 2, 2024
Time: 11:30 a.m.
Marvell Keynote: Navin Bishnoi, Country Head
Where to Find Us
IEEE International Symposium on VLSI Design and Test
Vellore Institute of Technology, Vellore, INDIA
September 1-3, 2024
Recent News
Marvell Introduces 1.6 Tbps LPO Chipset to Enable Optical Short-reach, Scale-up Compute Fabric Interconnects
Dec 10, 2024
Marvell Unveils Industry’s First Coherent-lite 1.6 Tbps O-band-optimized DSP for Data Center Campus Connectivity
Dec 10, 2024
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